Much has been written recently about the new OpenVPX standard known as VITA 65. This article provides an introduction to the structure of the specification. In order to define a system, it’s important to understand how to properly navigate through and decipher the different sections of the specification and its lexicon. Part two, a follow-on article scheduled for the November issue, will discuss how VITA 65 enables a user to build OpenVPX systems by combining slot and backplane profiles that support the establishment of an end system topology.

The OpenVPX standard has been brought to fruition through an intense effort driven first outside, then subsequently within the OpenVPX VITA Working Group. In a few months, a short list of companies and a team of dedicated industry veterans have brought us a 400+ page document that provides concepts and methods to describe system topologies using a new breed of serial fabric technologies and high-speed backplanes.

As discussed in recent articles, OpenVPX is based on prior VITA standards that initially addressed VPX, including VITA 46.0 and VITA 46.1. These standards formed a good base to allow the design and implementation of new high-speed, high-power systems, but they fell short when it came to fostering interoperability among offerings from different manufacturers of VPX boards and backplanes. So off on a quest went these VPX Knights—a new standard they sought, to alleviate these plights. Contending with MultiGig-2 wafer-based connectors good for data rates up to 10 Gbit/s and new backplane materials, including FR-408 and Nelco 4000-13SI, OpenVPX is taking us to new data transfer rates where we have not gone before (Figure 1).

SerDes-based physical interfaces supporting baud rates of 3.125, 5.0 and 6.25 Gbit/s are now common within the OpenVPX Module and Backplane lexicon. OpenVPX has generated a well structured specification volume, which at first glance would send Don Quixote back to the windmill. Introducing a new set of terms for describing lane-based point-to-point interconnects, the document quickly grew large driven by the unique topology required of each backplane described, and using equation-based formulas that specify Slot, Module and Backplane profiles.

OpenVPX - the Standard

The standard was created to allow for definition of system topologies and to promote interoperability. The specification is divided into 16 sections. Section One covers structure and defines terminology. Key Words are defined. The concepts of Profile Names are introduced and are summarized in Figure 2.

Slot (SLT) in Types: Payload (PAY), Peripheral (PER), Switch (SWH) and Storage (STO).

Module (MOD): Same Attributes as Slot but specific to the module (board) and defines the protocol associated with the ports.

Backplane (BKP) in Types: CEN, DIS, HYB, BRG, where:

• Central (Star)

• Distributed (Mesh)

• Hybrid (VME & VPX)
• BRG (Bridge, e.g., parallel VME to VPX)

Naming conventions for profiles are described to allow a user to create a name to define specific Module, Slot and Backplane profiles. Figure 3 is an example of a 3U payload slot profile with one fat pipe data plane, two fat pipe expansion planes and two ultra thin pipe control planes. All the additional attributes are found in the document in Section 14.2.2 of VITA 65. Module profiles and backplane profiles follow a similar naming convention that always includes the section number where the profile is defined in full detail.

Section two of the VITA 65 standard addresses compliance, which is an important topic since it describes how one must consider and comply with over 400 rules, permissions and recommendations. These requirements have been created to ensure interoperability between a backplane and the chosen module that one is about to plug into a defined OpenVPX Slot. Every VPX rule also has a compliance requirement that must be documented and established by one of four methods. These four compliance methods are defined within the OpenVPX standard as follows:

Inspection: The Inspection method primarily uses a static, visual means to demonstrate conformity.

Demonstration: The Demonstration method primarily uses a dynamic, visual means of showing functionality to demonstrate conformity. While test equipment may be required as part of the demonstration setup, measurements are typically not required.

Analysis: The Analysis method primarily uses theoretical means to demonstrate conformity. Analysis 1063 input parameters may be based on component datasheet or empirically derived parameters.

Test: The Test method primarily uses physical measurements and test procedures to demonstrate 1073 conformity. The Testing method is necessary when inspection, demonstration and analysis 1074 methods are inadequate, not supported by tools, or cost prohibitive.

Section three of VITA 65 discusses the Utility Plane, Power Distribution, System Control Signals, the Reference Clocks and the GPIO Signals. Pin Assignments are defined for J0/P0 and J1/P1. In addition, Section four covers the mechanical specifications. Described here are Slot Pitch, Connectors, Keying and RTM Connections.

In Section five, we are getting into the good stuff. This section covers the Fabric Protocols referenced today by VITA 65. Three major Protocols are defined, including Ethernet, Serial Rapid I/O (SRIO) and PCI Express (Table 1).

Sections six, seven and eight discuss Slot Profiles, Backplane Profiles and Module Profiles. Profiles are used as the central graphical representations of slots and backplanes in OpenVPX. With that said, it’s time to introduce a table called Profiles at a Glance that show the relationship between Slot, Module and Backplane profiles (Table 2).

Our Knights had found themselves banished from the Castle of OpenVPX until they could decipher the cryptic terminology to find the profile they were looking for, which would in turn enable them to find their path through the document—the path that would lead to the definition of a system. So armed with new knowledge they added royal tools to the document to help find the fair profile in distress, at a glance. These regal tools included very nice hyperlinked tables, which summarize available 6U Module Profiles in Table 11.2-1, and a 6U Module to Backplane Profile reference Table 11.2.2-1. The 3U tables are Table 15.2-1 and Table 15.2.2, specifying similar information for the 3U form factor. These tables are a great Module and Backplane navigational reference. Having deciphered the clues, they can now read the tables, one example of which is shown in Table 3.

Table 1
Summary of fabric protocols that can be used in OpenVPX

Table 3
VITA 65 establishes a family of 3U and 6U standard backplanes for development applications. Each backplane is comprised of a number of slot profiles which in turn correspond to various module profiles. This chart summarizes all the defined 6U backplane profiles and shows the module profiles that are compatible with the different slots that comprise each of the 15 different 6U backplane profiles.

Sections 10, 11 and 12 define 6U Slot, Backplane and Module Profiles respectively, while sections 14, 15 and 16 specify 3U Slot, Backplane and Module Profiles.

Other new concepts include the definition of Lanes, Channels, Ports and Pipes to describe how bidirectional serial lanes are grouped into different width channels. Pipes, for example, come in different sizes:

• Ultra Thin Pipe = 1 Lane
• Thin Pipe = 2 Lanes
• Fat Pipe = Four Lanes
• Double Fat Pipe =8 Lanes
• Quad Fat Pipe = 16 Lanes

What Does OpenVPX Do for the System Architect?

The specification gives the system designer a set of terms, a common language if you will, to describe a system uniquely. The syntax defined uses graphical icons that allow the visualization and description of the system topology. The definition of slot and module profiles establishes rules for mapping pins to slots.

Systems are described by the backplane profile that is comprised of a set of slot profiles. A backplane is simply a set of interconnected slot profiles where each pipe in one slot is mapped to a pipe in a second slot. This point-to-point mapping results in a unique topology for each backplane profile. It is unique because the lane pairs in a serial fabric will be connected point-to-point as required. The backplane in Figure 4 is full mesh, made up of five instances of Payload slot profile SLT-PAY-4F 10.3.1, connected in slots one through five. Each slot has a fat pipe connection to each of the other four slots creating a full mesh as shown in Figure 4.

In closing, one other navigational tip would be useful to note about profiles. Below is a Payload Slot profile. Note that the planes are described from top to bottom of the profiles and are associated with colors. However, the color key for the slot profiles is never explicitedly defined within the VITA 65 document nor has the convention of working down from the top of the connector to assign planes ever been explicitedly explained. Rather, these conventions are only implied and left for the reader to figure out on his or her own. Take for example the following 3U slot profile:

SLT3-PAY-2F1F2U-14.2.1

Color Code Key:

Yellow - Data Plane
Blue - Expansion Plane
Green - Control Plane

The first two yellow data plane ports are described by the first field as 2F, shown in yellow representing two fat pipes. The second field, 1F, describes the expansion plane in blue with one fat pipe. Finally, the green section represents the 3rd field, and the 3rd position down in the connector, representing the Control Plane shows 2U; two ultra thin pipes used for Ethernet connections. These can be followed in the slot profile diagram in Figure 5 giving the adventurous reader a more convenient means of following the formula and being able to compare it quickly with other profile diagrams.